[libre-riscv-dev] [isa-dev] Re: SV / RVV, marking a register as VL.

lkcl luke.leighton at gmail.com
Thu Sep 5 00:03:35 BST 2019


2.1.4 pack, all variants, and all permutations of all possible bitwidths of all src and dest operands, are also provided by SimpleV, using an element width override and suitable VL on a single opcode, either C.MV or its pseudo aliases (add rd rs1 x0).



More information about the libre-riscv-dev mailing list