[libre-riscv-dev] [isa-dev] Re: SV / RVV, marking a register as VL.

lkcl luke.leighton at gmail.com
Wed Sep 4 22:12:03 BST 2019

On Thursday, September 5, 2019 at 4:13:36 AM UTC+8, Jacob Lifshay wrote:
> On Wed, Sep 4, 2019, 09:20 lkcl <luke.l... at gmail.com> wrote:
> Rats.
> [snip]
> Anyone any ideas or solutions?
> I still think the full-function vectorization is workable, will explain in more detail in follow-up email.

Ok great. Can you also clarify or consider how ffirst, zeroing, lack of elwidth etc might be compensated for?

Also, if I understood correctly, with only 4 bits per register, a heck of a lot of SV capabilities is left out.

Those limitations, if correct, need a full evaluation.


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