[libre-riscv-dev] [isa-dev] Re: SV / RVV, marking a register as VL.

Jacob Lifshay programmerjake at gmail.com
Wed Sep 4 21:13:21 BST 2019

On Wed, Sep 4, 2019, 09:20 lkcl <luke.leighton at gmail.com> wrote:

> Rats.
> [snip]
> Anyone any ideas or solutions?

I still think the full-function vectorization is workable, will explain in
more detail in follow-up email.


More information about the libre-riscv-dev mailing list