[libre-riscv-dev] [isa-dev] Re: SV / RVV, marking a register as VL.
luke.leighton at gmail.com
Thu Sep 5 00:19:53 BST 2019
gorc seems to simply be the following:
grev t0, t1, rs2
or t0, t0, t1
Is that correct? If so, what significant general purpose savings are there which justify the additional opcode?
If an extremely commonly used algorithm exists for which gorc would reduce code size by significant margins compared to those two opcodes (grev, or) it would be good to list it.
More information about the libre-riscv-dev