[libre-riscv-dev] VBLOCK, reducing context size: use SVP format

[Luke Kenneth Casson Leighton]

On Sunday, September 1, 2019, Luke Kenneth Casson Leighton <lkcl at lkcl.net>
wrote


> The only question is, how to get it to apply to multiple instructions, and
> the answer is very simple: pick that information up from the very first
> instruction in the VBLOCK.
>

Jacob I just spotted that "missing" registers vd/vs1/2 are ORed from the
explicitly specified ones.

Is there anything strange about FMA that would cause strange interactions
and not create the required implicit vd flag?

Also because of the possibility of continuation of the state information to
other registers, I added vd to some of the 64 bit SVP formats.

This seems redundant for the first instruction but due to the reg numbers
being "picked" from the first instruction it is NOT redundant for
subsequent ones.

L.





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