[libre-riscv-dev] [Libre-silicon-devel] NLNet Funding Proposals for the Libre RISC-V SoC: call for participation

Staf Verhaegen staf at fibraservi.eu
Tue Sep 24 13:06:04 BST 2019

Luke Kenneth Casson Leighton schreef op di 24-09-2019 om 12:16 [+0100]:
> On Tue, Sep 24, 2019 at 9:55 AM Hagen SANKOWSKI <hsank at posteo.de> wrote:
> > The main difference between AMBI AXI and Wishbone is the streamingcapability. AXI can stream data, just with repetition stages, withouthandshake signals. So, it would be easier and more sustainable tobring-up Wishbone to the next level by standardize a similar streamingfeature. And yes, there are a lot of cores which using AMBA AXI whichhad to be partly re-written for Wishbone. But currently, there is noalternative, or as the German chancellor Merkel likes to say:"alternativlos". With added streaming feature to Wishbone, we would getan alternative full-featured SoC Bus and Designers could fix their badAMBA AXI bus interfaces..
> great: this sounds like a perfect *additional* Research Project whichsomeone [else] could put in a request for funding.  once it isavailable, we can look at converting the code over to use it, andconverting any peripherals to use it.
> or, if someone [else] wants to include the Libre RISC-V SoC peripheralset as a possible suite of examples to convert (which would helpjustify a budget of EUR 50,000) they are welcome to do so.
> the relevance of the streaming capability is that we need an I2S Audio Bus.
> i can help with a write-up: unfortunately i am hitting an _additional_limit of EUR 250,000 per person for overall projects submitted, socannot be the one to submit it.

Have yo guys looked at the pipeline feature of Wishbone B4 ? What is missing there to make streaming possible ?


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