[libre-riscv-dev] NLNet Funding Proposals for the Libre RISC-V SoC: call for participation

[Luke Kenneth Casson Leighton]

On Tuesday, September 24, 2019, Staf Verhaegen <staf at fibraservi.eu> wrote:

OK, let me mention I have for my Retro-uC currently nmigen Wishbone code.


Great!


>
> I use it to make an arbiter between JTAG and the CPU cores on the design
> (Z80, MOS6502 and Motorola 68000) that can do a read/write for each cycle.
> Plan is top commit code to my gitlab repo after ORConf.
> Dan from ZipCPU would say that I still have to formally verify the code
> though... .


Yes.  Ah it just occurred to me to get in touch with him again, see if he
would like to help with the formal proofs proposal.

Looks like you might get your "wish" after all, David :)

L.


> greets,
> Staf.
>
>

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