[libre-riscv-dev] [Libre-silicon-devel] NLNet Funding Proposals for the Libre RISC-V SoC: call for participation

[Staf Verhaegen]

Luke Kenneth Casson Leighton schreef op di 24-09-2019 om 13:12 [+0100]:
> On Tue, Sep 24, 2019 at 1:06 PM Staf Verhaegen <staf at fibraservi.eu> wrote:
> > Have yo guys looked at the pipeline feature of Wishbone B4 ? What is missing there to make streaming possible ?
> 
> hagen mentioned (offlist) that the broadcast mode of wishbone b4 couldindeed be used.  he'd like to do a write-up / proposal and i am happyto help him review it.
> l.

OK, let me mention I have for my Retro-uC currently nmigen Wishbone code. I use it to make an arbiter between JTAG and the CPU cores on the design (Z80, MOS6502 and Motorola 68000) that can do a read/write for each cycle.
Plan is top commit code to my gitlab repo after ORConf.
Dan from ZipCPU would say that I still have to formally verify the code though... .

greets,
Staf.