[libre-riscv-dev] [Bug 63] queue (FIFO) library routine needed

[bugzilla-daemon at libre-riscv.org]

http://bugs.libre-riscv.org/show_bug.cgi?id=63

--- Comment #3 from yuda at berkeley.edu ---
(In reply to Luke Kenneth Casson Leighton from comment #2)
> http://bitsbytesgates.blogspot.com/2017/08/chisel-sharpening-verification.
> html?m=1
> 
> Hi,
> 
> Ok so the truth is, I find writing code from scratch so extraordinarily
> difficult that it is not just a "good idea" to have unit tests, I simply
> cannot write code e
> without them.
> 
> This is why we copied queue.py and language translated it, because its usage
> in ASICs means that even without unit tests it has been at least deployed.
> 
> The "graphs" that are mentioned as a requested feature are achievable very
> simply with yosys "show modulename" after conversion to verilog and
> read_verilog command.
> 
> They are extraordinarily useful and help avoiding making obvious costly but
> "logically high level language correct" design oddities.
> 
> Beyond that, honestly and plainly, for goodness sake write full coverage
> unit tests. The best ones are formal tests and nmigen has some for SyncFIFO.

OK, I see. I will let you know when it is been tested.

Best,
Yuda

-- 
You are receiving this mail because:
You are on the CC list for the bug.