[libre-riscv-dev] [isa-dev] [RFC] SV branch behaviour: augmentation to store results of conditional tests

[lkcl]

hmm, slightly scary: it's a 4R1W operation:

* read: src1, src2, pred1, pred2 (for non-zeroing)
* write: pred2

5R1W if VL is counted as a "register".

l.