[libre-riscv-dev] [isa-dev] [RFC] SV branch behaviour: augmentation to store results of conditional tests
brucehoult at sifive.com
Tue Sep 24 20:00:02 BST 2019
On Tue, Sep 24, 2019 at 6:36 AM lkcl <luke.leighton at gmail.com> wrote:
> i wanted to run by people an augmentation of standard scalar RISC-V branch, which is a little complex to explain.
> with SV, there are no vector opcodes, only scalar ones that are "augmented" with a hardware-level for-loop, and may - if the hardware implementor chooses - be parallelised.
> with two possible registers in a branch operation to provide "tag" context (src1 and src2), a lot can be done to provide augmentation options. the general idea is: if there are going to be multiple elements being compared, then, well:
> (a) make them predicated and
> (b) store the results of the comparisons and
> (c) change the decision on whether to "branch" to be dependent on *all* of the comparisons and
> (d) add fail-on-first data-dependency which can terminate the comparisons early
> where (c) can be modified to be one of 4 decisions:
> * all-tests-zero (NAND)
> * all-tests-one (AND)
> * at-least-one-test-is-zero (NOR)
> * at-least-one-test-is-one (OR)
You appear to have reversed NAND and NOR.
Google "consensual branches". This is a standard feature in SIMT
architectures, though seldom publicly documented. Yunsup's theses is a
When you convert SIMT to vectors it becomes a test on predicate masks.
In RVV I expect this would turn into using VPOPC and then comparing
against 0 or VL.
More information about the libre-riscv-dev