[libre-riscv-dev] Overall strategy RE transcendentals

[Hendrik Boom]

On Tue, Sep 10, 2019 at 04:28:45AM -0700, lkcl wrote:

> 
> Thus the best that can be done is to use Quantitative Analysis to work
> out which "subsets" - sub-Extensions - to include, and be as "inclusive"
> as possible, and thus allow implementors to decide what to add to their
> implementation, and how best to optimise them.

Let's see if I understand.

So there are multiple ways of implementing different instructions, 
ranging all the way from doing it entirely in software (which takes 
very little CPU space) through a series of operations (serial) within 
the CPU all the way to relly high speed parallelism.  Which of these 
are even feasible depends entirely on the operation itself.  Which are 
practical depends on time/area tradeoffs and those tradeoffs have to be 
decided based on the ultimate application domain.

So we are trying to clarify all this by collecting and creating 
multiple implementations of useful operations so there is effectively a 
library of proven techniques that a CPU designer can pick and choose 
between.

Some of these we actually implement ourselves, some we gather from 
elsewhere and some we leave undone.

And then finally (but in practice concurrently) we design a particular 
RISC-V design so that it can be realised in hardware.  This would be 
the practical proof-of-concept that gives others something to use, and 
shows still others that this project has produced useful components.

-- hendrik

Apologies for saying "we" and including myself, because I have done 
nothing tangible yet towards the project.  But I find it less 
estranging than saying "you".