[libre-riscv-dev] [isa-dev] Re: SV / RVV, marking a register as VL.

[Jacob Lifshay]

On Sun, Sep 1, 2019, 10:35 lkcl <luke.leighton at gmail.com> wrote:

>
>
> On Sunday, September 1, 2019 at 5:23:14 PM UTC+1, Jacob Lifshay wrote:
>
> came up with something, overnight:
>>> https://groups.google.com/forum/#!topic/comp.arch/l2nzme2sCR0
>>>
>>
>> Few comments:
>>
>> the SVPMode table needs to have all entries use different encodings (they
>> all currently encode to 0b00)
>>
>
> good catch - they're in the commentary below, but not the table.
> cut/paste error.
>
>
>> The encodings don't match the RISC-V long-instruction encodings (SVPMode
>> would need to be moved to accommodate the 1s and 0 needed to produce 48,
>> 64, 80, 96, and larger bit lengths).
>>
>
Oops, I had misremembered the number of 1s needed. Sorry.

Jacob