[libre-riscv-dev] [Libre-silicon-devel] NLNet Funding Proposals for the Libre RISC-V SoC: call for participation

[Luke Kenneth Casson Leighton]

On Mon, Sep 23, 2019 at 9:48 AM David Lanzendörfer
<leviathan at libresilicon.com> wrote:
>
> Hi Luke
> In order to be truly libre, you've got to remove AXI from the RISC-V
> implementation and replace it with TileLink or another bus, which isn't
> patented by a company.
> Also I would strongly discourage you from using ARM patented solutions,
> this might most certainly come back in the future to hunt you.

appreciated, david: the main issue that we have is, with implementing
a GPU and VPU and CPU all in one, it's going to be unavoidable to run
into 3D patents, Video patents, you name it, we'll be hitting it.
from ICubeCorp alone - one company that i know of for certain created
a similar "Hybrid" CPU/GPU/VPU, we'll be hitting up to *seventeen*
patents:
https://patents.google.com/?q=ICubeCorp&oq=ICubeCorp

broadcom's videocore IV, which is based on the ARC core (bought by
synopsys), likewise has a whole stack of patents: ARC's primary
business was - is - licensing identical to ARM except embedded and not
as high-profile, with specialisation in Video SIMD instructions.

to even *try* to avoid these is just completely pointless: the entire
design would be so hamstrung as to be utterly commercially useless,
and, worse than that, we'd be taking on far more work and would
completely miss the goal as a result, missing out on additional
funding opportunities that would enable us to actually get to first
silicon.

in short: if we're adding AXI to the list of patents to avoid, because
we take on the additional responsibility of avoiding patents, we also
have to add the entire MASSIVE list of other patents in Video
Acceleration, 3D Acceleration, processor core design, and so on, and
it's just completely impractical.

some alternative strategies present themselves:

(1) if a customer (licensee) is presented with a patent demand, we can
look at prior art and arrange for the patent to be invalidated.  we
have nothing to lose.  enough of these being successful will cause
large patent holders to freak out and back the hell off.

(2) join a patent pool.  like the linux foundation, except for
hardware.  the newly-formed Open 3D Graphics Alliance is a good place
to start from, here.

(3) get to first silicon, get chips sold, get investment, *then* fund
a new ASIC design that avoids all known patents.

bottom line: we have to be realistic, and pick the best technology for
the job.  TileLink, with its low level of adoption, Is Not It (and
using chisel3 is not an option for this processor).  Wishbone, whilst
we may need some wb2axi bridges in order to avoid having to do major
rewrites, just doesn't cut it as far as complex multi-way routing is
concerned.

l.