[libre-riscv-dev] Application for funding for RISC-V ISA development for Video Acceleration: Call for Participation

[Luke Kenneth Casson Leighton]

On Sun, Sep 22, 2019 at 8:21 AM Frieder Paape <frieder at paape.io> wrote:
>
> Hi Luke,
>
> as a german national I would be able to be the main submitter. However I am a software engineer with little to no experience in hardware projects ( which I'd like to change some day ). Therefore I could serve as a proxy and deal with administrative tasks. Is that what you're searching for?

hiya frieder, that's perfect.  will get it set up and put in the application.

you may be interested to know that there's actually very little in the
way of hardware "experience" needed, here.  we're writing the hardware
in python, and that task just simply will not take that long, anyway.
it's a *small* (but obviously essential) part of the project.  i would
anticipate that each instruction, due to the simplicity and that
they're "primitives" (ROR, GREVI etc.) would be about... a week
including unit tests, if that.  a "skilled" engineer could likely
implement each of them in under an hour.

the main focus of the effort is the assembly code (in... assembler,
duh :) ), the simulator (c++), libswscale (c), libx265, libx264,
ffmpeg, gstreamer - etc. etc.

in the simulator, the "opcode" will be simulated *in c* (or c++), so,
again, no actual hardware experience needed.

the "hotspots" to focus on - algorithms needing to be written in
assembler and thus used to "verify" if the proposed opcodes actually
are going to work - are CABAC, motion-estimation (for encode), and YUV
2 RGB.

so, beyond "adminstrative" tasks, you're more than welcome to actually
help out (and receive donations for doing so).

thank you,

l.