[libre-riscv-dev] [isa-dev] 3D Matrix-style operations / primitives

lkcl luke.leighton at gmail.com
Wed Sep 18 20:19:57 BST 2019

hi stephen, something weird (again), your message didn't get through, 
here.  the Libre RISC-V SoC extends the 32-entry regfile to 128 64-bit regs 
per file, with the ability to subdivide them down to the byte-level in a 
SIMD-like fashion but actually more like a c typecast/union of uint8_t[], 
uint16_t[]], uint32_t[] and uint64_t[] arrays.


Stephen Fuld SFuld at alumni.cmu.edu.invalid via 
<https://support.google.com/mail/answer/1311182?hl=en> googlegroups.com 

> and so if we were to have a (parallelised) MV.swizzle or other primitive 
that could span (jump) across some of those, we'd have the basics.

A few comments.

This requires more than 16 registers, as the 4x4 matrix takes 16 and 
presumably the determinant (result) takes another.

You want to do inverse, but not all matrices are invertible.  How do 
propose to handle that.

Determinant is certainly doable, but it seems even more complicated than 
the complex multiply and divide I asked about in another thread.  AFAIK, 
no CPU does even those.

> how do you go about analysing this?  has research like this been done 
before, into designing an ISA based around matrix multiplication (not so 
much revolving around SIMD, more around Vector Architectures like Cray)?

I vaguely recall some graphics oriented chip doing 4x4 matrix multiply 
to speed a common graphics transform, but I don't remember any details. 

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