[libre-riscv-dev] [isa-dev] Re: SV / RVV, marking a register as VL.

[Jacob Lifshay]

On Sun, Sep 1, 2019, 07:34 lkcl <luke.leighton at gmail.com> wrote:

>
>
> On Saturday, August 31, 2019 at 3:57:20 PM UTC+1, lkcl wrote:
>
>>
>> i've been trying to think how to get that down further, for some time.
>>
>
> came up with something, overnight:
> https://groups.google.com/forum/#!topic/comp.arch/l2nzme2sCR0
>

Few comments:

the SVPMode table needs to have all entries use different encodings (they
all currently encode to 0b00)

The encodings don't match the RISC-V long-instruction encodings (SVPMode
would need to be moved to accommodate the 1s and 0 needed to produce 48,
64, 80, 96, and larger bit lengths).

Jacob