[libre-riscv-dev] 8x EUR 50, 000 NLNet Grant Applications submitted: participation welcome
luke.leighton at gmail.com
Sun Sep 29 08:03:32 BST 2019
eight separate EUR 50,000 NLNet proposals have now been submitted, each
having their own EU team member thus satisfying the bureaucratic conditions
set by the EU Horizon 2020 Programme. The original EUR 5m Grant, No
825310, was negotiated with the kind assistance of NGI.eu
progress of the applications process will be reported under the "Community"
thread (please remove isa-dev and sw-dev cc's if replying with questions).
* any University may be the recipient of donations once a given Grant is
* any individual, anywhere in the wordl, may likewise be the recipient
however it will *NOT* be in the form of "Salary", it will be
*tax-deductible* Charitable Donations, where NLNet's International
Accountant should be able to help advise *your* Accountant, if there are
any questions or issues.
the general-purpose ones which will commercially and strategically benefit
the entire RISC-V Community are:
- general-purpose instructions (similar to NEON/AVX) designed for video
acceleration, plus associated assembler, upstreamed into ffmpeg, libx264,
libvpx, libx265 etc.
- port of Mesa 3D RADV Vulkan Driver to RISC-V, with
staggered-capability accelerated instructions, and subsets of the same with
fall-back to full software-only capability, suitable for a wide and diverse
range of platforms, right the way from ultra-low-power embedded to full
modern GPU territory.
- OpenCL driver for RISC-V, dove-tailing with the work done on RADV (and
the Video Extension) which will have significant overlap at the ISA level.
- an improvement to the Wishbone B4 Standard, to be submitted to its
maintainers, to add "streaming" capability (with optional embedding of
timecode stamps for audio and video).
- formal write-up and upstream submission of the various RISC-V
Standards developed over the past 24 months, including development of full
Conformance Test Suites. this includes Zfpacc, Ztrans*, Simple-V, a
MV.X/MV.swizzle instruction, specialist vector operations (dotproduct,
S/LERP, normalise), Bitmanip extensions required to make SV a full peer of
RVV when it comes to predicate masking, and other specialist 3D opcodes.
these will all be needed by the above Software Drivers (OpenCL in
particular will be critically dependent on Ztrans*)
if there is a desire by any member of the RISC-V Community to actively
include RISC-V Vector Extension (RVV) in any of these, then you are welcome
to participate however will need to not only provide your own source of
funding but also actively sponsor the relevant project as well (so as to
avoid - unreasonably - burdening the available *Charitably-Donated* budget
from NLNet and other active sponsors).
thanks to NLNet's Charitable Foundation Status
(https://nlnet.nl/foundation), such sponsorship is tax-deductible by
Corporations, so there is not even any financial cost for any Corporation
to assist with the above strategic and commercially valuable projects.
as many of them are either based on LLVM (which already has a WIP RVV port,
by Robin Kruppe) or need to be written in assembler (RVV already has a
spike simulator and binutils RVV support), it is *not* necessary to wait
for other project dependencies (such as the gcc port, below).
it is also a good time to remind RISC-V Foundation Members of their
obligation under the Charter Agreement which will have been signed and
*2.2 Support for RISC-V Objectives. During the term of its membership in*
*Foundation, Member is expected to support the free and open design,
*improvement of the RISC-V ISA, together with its software and hardware
ecosystem for use*
*in all computing devices.*
all of the above are Libre-Licensed Projects, and clearly can be seen to
advance RISC-V in several strategically-significant and
commercially-significant areas. if you would therefore like to assist and
meet this obligation, as well as accelerate clear commercial benefits that
your Organisation would receive from the advancement of these projects,
please do get in touch, privately or on the Community Forum.
the specialist projects submitted, which are relevant to the Libre-RISC-V
- gcc vectorisation and auto-vectorisation support for RISC-V Simple-V,
to be actioned alongside the RVV port, learning from the ARM SVE gcc port.
- "Formal Verification" unit tests for *all* modules, as part of
fullfilling the "trust" obligations of NLNet's Privacy and Enhanced Trust
Programme (https://nlnet.nl/PET). In simple terms: proof that
Pentium-style FPDIV bugs ain't happenin, and proof that there's no spying
- an ASIC Layout using https://lip6.fr coriolis2, work to be done in
parallel with chips4makers
- a 180nm port of NSXLIB, OpenRAM and the creation of a new GPIO Cell
Library, by https://chips4makers.io, to a TSMC 180nm fab, using a Shuttle
Service that costs only EUR 600 per sq.mm. with a single-core ASIC
expected to be around 20mm^2 in 180nm, we will have a first
(commercially-viable) 64-bit test chip for only USD 12,000, dual-issue
300-350mhz, and suitable for Robotics and other high-end Embedded purposes.
again, anyone anywhere in the world may be the recipient of donations for
the completion of sub-tasks on the list, within any of these projects. we
will have regular progress and news over the next 2-3 months.
any questions, please do remember to remove isa-dev and sw-dev. cc'ing
libre-riscv-dev is fine and welcomed. also feel free to contact me
privately if you would like to participate in any of the above.
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