[libre-riscv-dev] NLNet grant application EUR 50, 000 for gcc port on Libre RISCV Vectorisation

lkcl luke.leighton at gmail.com
Tue Sep 24 16:03:19 BST 2019


Summary: if anyone would like to be the recipient of donations direct from NLNet [1] for completing milestones on a gcc backend port to support the Libre RISCV Vectorisation Engine (SimpleV) please do get in touch, promptly.

Anyone may be the recipient, we do however need at least one EU Citizen (who does not have to be resident in the EU at the time) because NLNet is funded under the Horizon 2020 Programme. There is no contractual obligation or penalty.

The port itself will be based on the current scalar RISCV port, and at its simplest, the first milestone will be to support the subvector types (vec2, vec3, vec4) which are very similar to SIMD.

Beyond that we need full function vector and predicate analysis, which is where the fun really starts.

Ultimately the purpose of SV is not just to get vectorisation it is a way to compress code size as well.  LD/ST-MULTI is possible as a 48 bit or 64 bit opcode, by accident, with predication being possible as well, it can be used for function call context saving and restoring.

It is quite a fascinating research project. It is worth noting then that NLNet is happy to donate to a University or to an individual (just not to a Corporation).

The riscv-spike-sv simulator will be developed in conjunction with this project so there will be no need to run on FPGAs or have actual hardware, it can be done entirely in software.

Any questions please do ask, either here, or on libre-riscv-dev, or contact me offlist.


[1] https://nlnet.nl/PET/ EU Grant  No 825310 https://nlnet.nl/foundation/ charitable tax status agreements established, links available

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