[libre-riscv-dev] [Bug 186] Create decoder for SOC: Power ISA and RISC-V

[bugzilla-daemon at libre-riscv.org]

http://bugs.libre-riscv.org/show_bug.cgi?id=186

--- Comment #42 from Luke Kenneth Casson Leighton <lkcl at lkcl.net> ---
hiya michael,
http://lists.libre-riscv.org/pipermail/libre-riscv-dev/2020-March/004661.html

ok the minor_31 opcode is just absolutely ridiculous, so i took a look
at pages 1385-1386 of Version 2.07B and noticed that there are patterns
in the columns.  add occupies the entire LSB "01010" column for example.

sooOooo... what i propose is a two-level hierarchy as follows:

* pre-process the rows by
* first identifying the first 5 bits as keys (let's say N are identifed)
* splitting the rows into N groups (by 5-bit key)

then it becomes possible to create a case-of-case-statements, each with
a separate PowerDecoder(), "automatically" from those groups.

in fact, i suspect that it *might* be possible to specify how to decode
*all* of the instructions in this fashion, with some sort of "specification"
that says "these bits get decoded with this table", then "these bits get
decoded with this table" etc. etc. in a cascade.

i am quite tempted to suggest instead to split minor_31.csv into separate
minor_31_5LSBs.csv files rather than do it automatically.

what's your thoughts there?

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