[libre-riscv-dev] [Bug 186] Create decoder for SOC: Power ISA and RISC-V

[bugzilla-daemon at libre-riscv.org]

http://bugs.libre-riscv.org/show_bug.cgi?id=186

--- Comment #43 from Luke Kenneth Casson Leighton <lkcl at lkcl.net> ---
ok i committed some experimental code (if False:) which gives
the general idea, where PowerDecoder would iterate recursively
through sub-encoders that have the bit-width specified that
they are to look into.

minor_19 i altered from anton's original so that the "19_valid"
check is not needed.  however, again, like 31, because it is
10 bits wide, it now needs a "pre-processing" stage, taking
the bottom 5 bits, first, and creating a list-of-lists which
act as *another* level of recursive hierarchy.

unfortunately for Power ISA, it looks like they have something
like four, five or even six levels of these decoders, i.e.
5 separate areas of the opcode that you must decode sequentially
in order to work out the "true" operation.

if you try to "flatten" any of those, you end up with the horrible
129-bit OR gates (!)

anyway.  do let me know what you think, michael.

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