[libre-riscv-dev] [Bug 186] Create decoder for SOC: Power ISA and RISC-V

[bugzilla-daemon at libre-riscv.org]

http://bugs.libre-riscv.org/show_bug.cgi?id=186

--- Comment #44 from Jacob Lifshay <programmerjake at gmail.com> ---
(In reply to Luke Kenneth Casson Leighton from comment #43)
> if you try to "flatten" any of those, you end up with the horrible
> 129-bit OR gates (!)

That may not be that big of a problem, since yosys should change that to a
4-level tree of 3 or 4-input OR gates.

One other option is to use one or more ROMs for parts of the decoding process,
since they are optimized for those cases where you need dense lookup tables.
Something like a 7-bit address would work fine.

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