[libre-riscv-dev] [Bug 186] Create decoder for SOC: Power ISA and RISC-V

[bugzilla-daemon at libre-riscv.org]

http://bugs.libre-riscv.org/show_bug.cgi?id=186

--- Comment #45 from Luke Kenneth Casson Leighton <lkcl at lkcl.net> ---
(In reply to Jacob Lifshay from comment #44)
> (In reply to Luke Kenneth Casson Leighton from comment #43)
> > if you try to "flatten" any of those, you end up with the horrible
> > 129-bit OR gates (!)
> 
> That may not be that big of a problem, since yosys should change that to a
> 4-level tree of 3 or 4-input OR gates.

when it comes to synthesis: true. you can tell however that this ISA was not
"designed", it organically grew.



> One other option is to use one or more ROMs for parts of the decoding
> process, since they are optimized for those cases where you need dense
> lookup tables. Something like a 7-bit address would work fine.

i think... these are effectively Consts being assigned in a suite of Case
statements, i have no idea if a ROM lookup would be more efficient, the address
decode tree might actually be more gates, whereas these minor opcodes, they are
a sparsely populated table with a considerable number of blanks, and a number
of "early outs" if you know what i mean.

so i suspect that a full address lookup cascade would be a lot more gates.

i kinda like the code compactness of the Switch and Case system that Michael
created, loading from csv files.  it's kinda hilarious - reminds me of when i
took the .txt file version of Microsoft's SMB Spec and literally spewed out c
code structs and associated network parser from it :)

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