[libre-riscv-dev] [Bug 186] Create decoder for SOC: Power ISA and RISC-V

[bugzilla-daemon at libre-riscv.org]

http://bugs.libre-riscv.org/show_bug.cgi?id=186

--- Comment #46 from Michael Nolan <mtnolan2640 at gmail.com> ---
(In reply to Luke Kenneth Casson Leighton from comment #43)
> ok i committed some experimental code (if False:) which gives
> the general idea, where PowerDecoder would iterate recursively
> through sub-encoders that have the bit-width specified that
> they are to look into.
> 
> 
> anyway.  do let me know what you think, michael.

So I tried this in 8af7da, and it works... Current minor_31_decoder (split 5
bits and 5 bits):
   Number of cells:                787
Longest topological path in top (length=16)


Old way: 
   Number of cells:                972
Longest topological path in top (length=15)

So it's a little smaller, but a little deeper

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