[libre-riscv-dev] [Bug 186] Create decoder for SOC: Power ISA and RISC-V

[bugzilla-daemon at libre-riscv.org]

http://bugs.libre-riscv.org/show_bug.cgi?id=186

--- Comment #47 from Luke Kenneth Casson Leighton <lkcl at lkcl.net> ---
(In reply to Michael Nolan from comment #46)

> So I tried this in 8af7da, and it works... 

excellent!

> Current minor_31_decoder (split 5
> bits and 5 bits):
>    Number of cells:                787
> Longest topological path in top (length=16)

ok that's surprisingly not a lot smaller, i would have expected it to drop
quite a lot.

should work great on minor_19 as well.

anyway: with the ability to do "sub-decoding" the idea that i had was to
literally chain the entire lot together, in a tree of decoders, specified
at the top level like in that "if False:" block.

the idea being, we just have to write a tree-like array of specifications,
pass that into *one* PowerDecoder, and it will (recursively) pass the next
part of the spec-array to more PowerDecoder instances.

otherwise we need to set that up "by hand"... with a top-level hand-coded
Switch / Case statement, which, once done, i guarantee you will go,
"hmm, this looks pretty much exactly like a PowerDecoder instance" :)

you want to have a go at that?

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