[libre-riscv-dev] [Bug 186] Create decoder for SOC: Power ISA and RISC-V

[bugzilla-daemon at libre-riscv.org]

http://bugs.libre-riscv.org/show_bug.cgi?id=186

--- Comment #48 from Luke Kenneth Casson Leighton <lkcl at lkcl.net> ---
hiya michael i've just spotted that minor_19.csv isn't quite ready yet,
i'm working on getting it up to scratch so that it's in a position
to do the hierarchical tree idea.  i may just "cheat" and create
a minor_19_00000.csv table.

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