[libre-riscv-dev] [Bug 186] Create decoder for SOC: Power ISA and RISC-V

[bugzilla-daemon at libre-riscv.org]

http://bugs.libre-riscv.org/show_bug.cgi?id=186

--- Comment #49 from Michael Nolan <mtnolan2640 at gmail.com> ---
(In reply to Luke Kenneth Casson Leighton from comment #47)

> 
> the idea being, we just have to write a tree-like array of specifications,
> pass that into *one* PowerDecoder, and it will (recursively) pass the next
> part of the spec-array to more PowerDecoder instances.
> 
> otherwise we need to set that up "by hand"... with a top-level hand-coded
> Switch / Case statement, which, once done, i guarantee you will go,
> "hmm, this looks pretty much exactly like a PowerDecoder instance" :)
> 
> you want to have a go at that?

I have something like that semi-working in b2bb2b, but it doesn't include
extra.csv or minor_19_00000. 

(In reply to Luke Kenneth Casson Leighton from comment #48)
> hiya michael i've just spotted that minor_19.csv isn't quite ready yet,
> i'm working on getting it up to scratch so that it's in a position
> to do the hierarchical tree idea.  i may just "cheat" and create
> a minor_19_00000.csv table.

I get what extra.csv is for, though I'm not entirely sure how to integrate it
with the decoder. What is minor_19_00000.csv for though?

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