[libre-riscv-dev] [Bug 186] Create decoder for SOC: Power ISA and RISC-V

[bugzilla-daemon at libre-riscv.org]

http://bugs.libre-riscv.org/show_bug.cgi?id=186

--- Comment #50 from Luke Kenneth Casson Leighton <lkcl at lkcl.net> ---
(In reply to Michael Nolan from comment #49)
> (In reply to Luke Kenneth Casson Leighton from comment #47)
> 
> > 
> > the idea being, we just have to write a tree-like array of specifications,
> > pass that into *one* PowerDecoder, and it will (recursively) pass the next
> > part of the spec-array to more PowerDecoder instances.
> > 
> > otherwise we need to set that up "by hand"... with a top-level hand-coded
> > Switch / Case statement, which, once done, i guarantee you will go,
> > "hmm, this looks pretty much exactly like a PowerDecoder instance" :)
> > 
> > you want to have a go at that?
> 
> I have something like that semi-working in b2bb2b, 

nice, will take a look.

> but it doesn't include
> extra.csv or minor_19_00000. 

ok.


> I get what extra.csv is for, though I'm not entirely sure how to integrate
> it with the decoder.

yeah it is effectively at the same "level" as the major opcodes, and needs to
be done.. mmmm... before them?

in effect it is extra case statements that need to go into major.csv.

the only "problem" is, the widths are different.  therefore, we need to have
*two* switch statements.

i *think* this is doable by making all args of PowerDecode into lists,
disabling the "default" switch, and initialising the "default" at the
beginning.

> What is minor_19_00000.csv for though?

just as extra.csv is to be added in at the same level as major.csv,
minor_19_00000 is likewise needing to be added to minor_19 ad a 2nd set of
switches, but with *different* widths.

hence the idea of making PowerDecode args into lists then putting a for-loop
around the switch generation.

what do you think?

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