[libre-riscv-dev] [Bug 186] Create decoder for SOC: Power ISA and RISC-V

[bugzilla-daemon at libre-riscv.org]

http://bugs.libre-riscv.org/show_bug.cgi?id=186

--- Comment #41 from Luke Kenneth Casson Leighton <lkcl at lkcl.net> ---
i saw you added minor_30.csv (great), i added 58 and 62.
https://github.com/antonblanchard/microwatt/blob/master/decode1.vhdl

hmm i think perhaps we could do instead with a class rather than
explicit members of PowerDecoder, i moved them into PowerOps.
perhaps later PowerOps might best be derived from Record, although
whitequark is being quite intransigent about how Record should be
created (and used), which causes us quite a lot of problems in using
it.  leaving that aside and moving on...

when doing nop, attn and SIM_CONFIG, these are explicit single-ops
that need assignment in a derivative of PowerDecoder

https://github.com/antonblanchard/microwatt/blob/master/decode1.vhdl#L391

in VHDL, "&" appears not to be the logical "AND" operator, it appears to be
"append together".  line 375 for example.

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