[libre-riscv-dev] Power ISA and associated Challenges
Luke Kenneth Casson Leighton
lkcl at lkcl.net
Sun Mar 1 16:01:27 GMT 2020
whooaa, i just took a look at the opcode 31 decoder in yosys: waaa
that's a big block.
the problem is that the selection field for opcode 31 is 10 bits long,
and does not appear to be regularised in any obvious way:
that's a *lot* of operations. ISEL and ADD are pretty obvious: ISEL
(first 5 bits 0b01111) for example, however LD/ST are a dog's dinner
that will be what people *may* be referring to about decode
complexity. what yosys creates by default for that, based on a
straight "case" statement loop, is just a mess: in one case it creates
a 129-bit OR and in another it creates a 127-bit OR gate. (!!)
we really can't have that.
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