[libre-riscv-dev] Power ISA and associated Challenges

[Luke Kenneth Casson Leighton]

whooaa, i just took a look at the opcode 31 decoder in yosys: waaa
that's a big block.

the problem is that the selection field for opcode 31 is 10 bits long,
and does not appear to be regularised in any obvious way:
https://libre-riscv.org/openpower/isatables/

that's a *lot* of operations. ISEL and ADD are pretty obvious: ISEL
(first 5 bits 0b01111) for example, however LD/ST are a dog's dinner
mess.

that will be what people *may* be referring to about decode
complexity.  what yosys creates by default for that, based on a
straight "case" statement loop, is just a mess: in one case it creates
a 129-bit OR and in another it creates a 127-bit OR gate.  (!!)

we really can't have that.

l.