[Libre-soc-bugs] [Bug 865] implement vector bitmanip opcodes

[bugzilla-daemon at libre-soc.org]

https://bugs.libre-soc.org/show_bug.cgi?id=865

--- Comment #16 from Andrey Miroshnikov <andrey at technepisteme.xyz> ---
I made the pseudo-code, by PyWriter doesn't like it:
    if (RB) = 0 then RT <- 0
    else                  RT <- (RA)

    if (RB) = 0 then mask <- (RB)
    else                  mask <- 0xffffffffffffffff

    RA <- RA & mask
    if (mode&1) = 1 then a1 <- (RA)
    else                  a1 <- (~RA)

    mode2 <- (mode >> 1) & 0b11
    if mode2 = 0 then a2 <- -(RA)
    if mode2 = 1 then a2 <- (RA)-1
    if mode2 = 2 then a2 <- (RA)+1
    if mode2 = 3 then a2 <- ~((RA)+1)

    a1 <- a1 & mask
    a2 <- a2 & mask
    mode3 <- (mode >> 3) & 0b11
    if   mode3 = 0 then RT <- a1 | a2
    if mode3 = 1 then RT <- a1 & a2
    if mode3 = 2 then RT <- a1 ^ a2

The PowerISA doc said switch statements are supported, but I haven't checked if
PyWriter supports them.
I'll continue on this tomorrow.

-- 
You are receiving this mail because:
You are on the CC list for the bug.