[Libre-soc-bugs] [Bug 737] in-order single-issue Power ISA 3.0 core

[bugzilla-daemon at libre-soc.org]

https://bugs.libre-soc.org/show_bug.cgi?id=737

--- Comment #2 from Luke Kenneth Casson Leighton <lkcl at lkcl.net> ---
https://git.libre-soc.org/?p=soc.git;a=blob;f=src/soc/regfile/regfiles.py;hb=HEAD

regfiles are created either binary-addressed or unary-addressed,
core.py shows how:

 267         # select the required read port.  these are pre-defined sizes
 268         rfile = regs.rf[regfile.lower()]
 ...
 329                 if rfile.unary:
 330                     rens.append(addr_en)
 331                 else:
 332                     addrs.append(addr_en)
 333                     rens.append(rp)

therefore, for creating a bitvector class, the Regfiles.rf dict can be
enumerated, and a series of setter/getter ports added.

funnily enough, a good class to use for that would be... an unary-addressable
regfile!

probably: RegFileArray(32, 1) - 3 regs but 1 bit per reg.

there will only be one bit per "reg", but enough ports need to be added
so that issue can read all it needs and write all bits from all operands
simultaneously.

by that i mean:

* for LD with update there are 2 reads and 2 write regs (GPRs)
* ST with update, 3 reads 1 write
* mul-accumulate 3 read 1 write

therefore the INT reg bitvector "regfile" will need to be 2W
but only 1R because although you want to be able to write 2
bits simultaneously (LD-with-update) only the Issuer will be
reading the global vector.

similar analysis for CR file.

-- 
You are receiving this mail because:
You are on the CC list for the bug.