[Libre-soc-bugs] [Bug 737] in-order single-issue Power ISA 3.0 core

[bugzilla-daemon at libre-soc.org]

https://bugs.libre-soc.org/show_bug.cgi?id=737

--- Comment #1 from Luke Kenneth Casson Leighton <lkcl at lkcl.net> ---
https://git.libre-soc.org/?p=soc.git;a=blob;f=src/soc/simple/core.py;hb=HEAD

core.py can likely be used as-is with no modifications, as long as the
issue is stalled at issue phase itself, if the register "write outstanding"
bitvector has all the bits clear.

process:

* decode detects register numbers for write and read
  and creates a unary bitvector mask for each.
  - add r5, r7, r3 would create:
  - read vector of 0b0000000010001000
  - wr   vector of 0b0000p00000100000
* global WRITE vector is ANDed with instruction READ vector
  - this detects any RaW (Read after Write) hazards
  - if the AND has any bits set, the entire processor MUST stall
  - this instruction and all others must NOT be issued
  - if it is clear (on this or a future cycle) the instruction
    may proceed
* when the instruction proceeds the WRITE vector must be ORed
  into the GLOBAL write vector
* when an instruction completes, the bits that were set in
  the GLOBAL write vector must be cleared.
  - this can be done by hooking into the write port (snooping)
    of the regfile (PC update is done this way)

two things to note:

* be careful when both reading and writing to the same reg.
  the regfiles all have "operand forwarding" so it is technically
  possible to achieve, but watch out for the bitvector
* cancellation (exceptions) has to be thought through: anything
  still in the pipeline that was issued BEFORE the exception
  point has to be allowed to finish.
  strictly speaking if an exception could occur then no
  further instruction should be issued until the possibility
  of an exception has passed.  (i.e. stall)

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