[Libre-soc-bugs] [Bug 731] potential design oversight in Partitioned SimdSignal Cat/Assign/etc lhs/rhs

[bugzilla-daemon at libre-soc.org]

https://bugs.libre-soc.org/show_bug.cgi?id=731

--- Comment #4 from Luke Kenneth Casson Leighton <lkcl at lkcl.net> ---
ngggh i have this horrible feeling that the solution here, if the problem
is demonstrated to exist, involves a "collation" (AST temporary storage)
phase, a suite of mirror Cat/Part/Repl etc classes which keep track of
their Values, such that Assign may, once it is used, explicitly determine
what is LHS and which is RHS and *only then* perform the required
Partition submodule allocation.

given that the existing PartitionedCat and Repl etc. appear to be RHS-only
they need to be complemented with corresponding LHS classes, whereupon
Assign has what it needs.

drat.

solvable but complicated.

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