[Libre-soc-bugs] [Bug 731] potential design oversight in Partitioned SimdSignal Cat/Assign/etc lhs/rhs

[bugzilla-daemon at libre-soc.org]

https://bugs.libre-soc.org/show_bug.cgi?id=731

--- Comment #3 from Jacob Lifshay <programmerjake at gmail.com> ---
(In reply to Luke Kenneth Casson Leighton from comment #0)
> submodule designs for PartitionedCat, PartitionedRepl, PartitionedAssign
> etc. which may only cope at present with the AST Construct being on
> the rhs:

We won't have to worry about Repl, since nmigen only supports assigning to
Signals and Slice, Cat, and Part:
https://github.com/nmigen/nmigen/blob/177f1b2e40694da473fdb0d95f4f6b33f5ea12ab/nmigen/back/rtlil.py#L631

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