[Libre-soc-bugs] [Bug 731] potential design oversight in Partitioned SimdSignal Cat/Assign/etc lhs/rhs

[bugzilla-daemon at libre-soc.org]

https://bugs.libre-soc.org/show_bug.cgi?id=731

--- Comment #5 from Luke Kenneth Casson Leighton <lkcl at lkcl.net> ---
(In reply to Jacob Lifshay from comment #2)
> (In reply to Luke Kenneth Casson Leighton from comment #1)
> > thus, we conclude that for "lhs" mode there must be a *list of outputs*
> > rather than as is the case currently only a list of *inputs*.
> 
> Yup, having a list of outputs is exactly what I did in
> SwizzledSimdValue...That list (actually a dict from Signals to be assigned
> to to the computed values to assign to those Signals) is
> AssignSwizzle.outputs.

have you written the unit test first that confirms the work is necessary?

(also we do not chuck away existing code without serious justification,
we morph existing code with incremental changes)

> > determining which mode to use, unfortunately, cannot be determined until
> > the actual Assignment takes place!
> > 
> > therefore, Assignment must actually perform an analysis of its lhs and
> > rhs arguments and set which mode (lhs or rhs) they are set to!
> 
> Well, actually, the exact same object can be used as both a lhs and a rhs:
> a = Signal(16)
> s = a[5]
> b = Signal()
> m.d.comb += [b.eq(s), s.eq(1)]

if i am following correctly this assumes throwing away existing tested code
and replacing it with unauthorised code which was not discussed whether it
was needed, nor its design aspecymts discussed, before being written?
(if so this is a habit that you really, really need to break)

> I'm expecting that we will want to support a[3:5].eq(...) since that's very
> common iirc. 

the alternative which is a nuisance is to do Cat() construction darn it
that is LHS too.

> Assigning to Cat is very uncommon (I don't think we ever do it,
> but I could be wrong .. maybe as part of assigning to a Record?)

i use it a lot.  the PriorityPicker, some of the ALUs i think.
it is an extremely valuable technique that dramatically clarifies
graphviz diagrams.  there will not be that many though. oh wait...
the entirety of RecordObject, the Stage API... although perhaps
this is outside of the ALUs or there is a workaround.

good about Repl, of course makes no sense to assign LHS multiple
times.

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