[libre-riscv-dev] [Bug 268] nmigen does not seem to support write-through SRAM

[bugzilla-daemon at libre-riscv.org]

http://bugs.libre-riscv.org/show_bug.cgi?id=268

--- Comment #4 from Luke Kenneth Casson Leighton <lkcl at lkcl.net> ---
okaaay so that's write-port *priority*, not the same thing as write-*through*
capability.  you've got a (similar?) unit test kicking around, would you be ok
writing a similar one that checks if what is written can be read on the same
clock cycle?

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