[libre-riscv-dev] [Bug 268] nmigen does not seem to support write-through SRAM

bugzilla-daemon at libre-riscv.org bugzilla-daemon at libre-riscv.org
Fri Mar 27 13:45:23 GMT 2020


--- Comment #3 from Jacob Lifshay <programmerjake at gmail.com> ---
(In reply to Luke Kenneth Casson Leighton from comment #2)
> i think this was the basis of a unit test that jacob wrote, and he found that
> there was a definite bug in the nmigen Simulation.  i believe however it
> was a 2R1W arrangement.  jacob can you remember?

Found it:

nmigen bug:

Turned out that write conflicts weren't implemented as advertised, the buggy
feature (write port priority) was later removed:

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