[libre-riscv-dev] [Bug 268] nmigen does not seem to support write-through SRAM

[bugzilla-daemon at libre-riscv.org]

http://bugs.libre-riscv.org/show_bug.cgi?id=268

--- Comment #3 from Jacob Lifshay <programmerjake at gmail.com> ---
(In reply to Luke Kenneth Casson Leighton from comment #2)
> i think this was the basis of a unit test that jacob wrote, and he found that
> there was a definite bug in the nmigen Simulation.  i believe however it
> was a 2R1W arrangement.  jacob can you remember?

Found it:
https://salsa.debian.org/Kazan-team/simple-barrel-processor/-/blob/391d95f30bd99e37236af8fb95565809b7230e29/test/test_mem.py

nmigen bug:
https://github.com/m-labs/nmigen/issues/47

Turned out that write conflicts weren't implemented as advertised, the buggy
feature (write port priority) was later removed:
https://github.com/m-labs/nmigen/commit/a02e3750bfeba44bcaad4c5de8d9eb0ef055d9c6

-- 
You are receiving this mail because:
You are on the CC list for the bug.