[libre-riscv-dev] [Bug 268] nmigen does not seem to support write-through SRAM

bugzilla-daemon at libre-riscv.org bugzilla-daemon at libre-riscv.org
Fri Mar 27 10:55:40 GMT 2020


Luke Kenneth Casson Leighton <lkcl at lkcl.net> changed:

           What    |Removed                     |Added
                 CC|                            |programmerjake at gmail.com

--- Comment #2 from Luke Kenneth Casson Leighton <lkcl at lkcl.net> ---
i think this was the basis of a unit test that jacob wrote, and he found that
there was a definite bug in the nmigen Simulation.  i believe however it
was a 2R1W arrangement.  jacob can you remember?

You are receiving this mail because:
You are on the CC list for the bug.

More information about the libre-riscv-dev mailing list