[libre-riscv-dev] [Bug 268] nmigen does not seem to support write-through SRAM

[bugzilla-daemon at libre-riscv.org]

http://bugs.libre-riscv.org/show_bug.cgi?id=268

Luke Kenneth Casson Leighton <lkcl at lkcl.net> changed:

           What    |Removed                     |Added
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                 CC|                            |programmerjake at gmail.com

--- Comment #2 from Luke Kenneth Casson Leighton <lkcl at lkcl.net> ---
i think this was the basis of a unit test that jacob wrote, and he found that
there was a definite bug in the nmigen Simulation.  i believe however it
was a 2R1W arrangement.  jacob can you remember?

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