[libre-riscv-dev] [Bug 268] nmigen does not seem to support write-through SRAM

[bugzilla-daemon at libre-riscv.org]

http://bugs.libre-riscv.org/show_bug.cgi?id=268

Staf Verhaegen <staf at fibraservi.eu> changed:

           What    |Removed                     |Added
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                 CC|                            |staf at fibraservi.eu

--- Comment #1 from Staf Verhaegen <staf at fibraservi.eu> ---
I may have overlooked something and write-through may actually be implemented.
I think the trick is to have both a read and a write port; have these port
share the same address signal and also do a read when you do a write (e.g. have
transparent read port which make the read port always enabled).

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