[libre-riscv-dev] [Bug 268] New: nmigen does not seem to support write-through SRAM

[bugzilla-daemon at libre-riscv.org]

http://bugs.libre-riscv.org/show_bug.cgi?id=268

            Bug ID: 268
           Summary: nmigen does not seem to support write-through SRAM
           Product: Libre-SOC's first SoC
           Version: unspecified
          Hardware: PC
                OS: Linux
            Status: CONFIRMED
          Severity: enhancement
          Priority: ---
         Component: Source Code
          Assignee: lkcl at lkcl.net
          Reporter: lkcl at lkcl.net
                CC: libre-riscv-dev at lists.libre-riscv.org
   NLnet milestone: ---

http://lists.libre-riscv.org/pipermail/libre-riscv-dev/2020-March/005453.html

we would like to have write-through capability in nmigen Memory.  when
one write-port writes, a read-port *in the same major cycle* is capable
of receiving that same data.

Staf mentions that the SRAM that he is doing makes that data available
on the *falling* edge (not on the exact same cycle).

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