[libre-riscv-dev] cache SRAM organisation

[Luke Kenneth Casson Leighton]

On Fri, Mar 27, 2020 at 9:46 AM Luke Kenneth Casson Leighton
<lkcl at lkcl.net> wrote:
>
> On Fri, Mar 27, 2020 at 9:40 AM Staf Verhaegen <staf at fibraservi.eu> wrote:

> > The nmigen Memory abstraction does not seem to allow a good representation of a write-through SRAM. AFAICS it does not allow to have the output of the read port be changed by what you write on the write port.
>
> urk, that's an important oversight.  we'll need to raise a bugreport
> with whitequark about it.

ok raised a bugreport here.

if nothing else, Staf, we just augment the SRAM with external MUX
logic, or we simply use SFFs for the RegFile.  it'll be big, but it
will work.

l.