[libre-riscv-dev] cache SRAM organisation

[Staf Verhaegen]

Luke Kenneth Casson Leighton schreef op wo 25-03-2020 om 15:53 [+0000]:
> On Wed, Mar 25, 2020 at 1:46 PM Staf Verhaegen <staf at fibraservi.eu> wrote:
> a workaround (fallback position) is, we use DFF latches.  i created a"bypass latch" function which creates DFF latches with such acombinatorial bypass: we actually use them quite a lot (includingbetween pipeline stages so that we can programmatically cut the numberof pipeline stages in half at the flick of a switch).

Would like to make separate side remark here. In ASICs MUXes are relative expensive gates with respect to delay and power. So if this principle is generally applied over the whole design it will make it difficult to make a chip that is competitive in power/performance compared to ARM/x86 CPUs.
In general if you are trying to optimize power/performance of your chip the KISS (keep it simple stupid) is your friend. In that respect your complex dual ISA decoder will have a power cost.

greets,
Staf.