[libre-riscv-dev] cache SRAM organisation

[Luke Kenneth Casson Leighton]

On Thursday, March 26, 2020, Staf Verhaegen <staf at fibraservi.eu> wrote:

>
> Would like to make separate side remark here. In ASICs MUXes are relative
> expensive gates with respect to delay and power. So if this principle is
> generally applied over the whole design it will make it difficult to make a
> chip that is competitive in power/performance compared to ARM/x86 CPUs.


just the ALU pipeline registers.  we felt that the advantage of being able
to drop to say 500mhz and halve the number of pipeline stages to say 5, and
also be able to ramp up to 1.6ghz and double bavk up to 10 stages, was
worth considering.


> In general if you are trying to optimize power/performance of your chip
> the KISS (keep it simple stupid) is your friend. In that respect your
> complex dual ISA decoder will have a power cost.


sigh yes i know.  however i do not know if you've seen the POWER ISA
decoder, it is *five* levels deep in some places, decoding different field
ranges in a dependent cascade!

adding RV would be trivial by comparison!

 but yes we are generally getting the message from various sources that
dual ISA isn't a good idea.

l.



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