[libre-riscv-dev] cache SRAM organisation

[Staf Verhaegen]

Luke Kenneth Casson Leighton schreef op do 26-03-2020 om 13:05 [+0000]:
> On Thursday, March 26, 2020, Staf Verhaegen <staf at fibraservi.eu> wrote:
> > Would like to make separate side remark here. In ASICs MUXes are relativeexpensive gates with respect to delay and power. So if this principle isgenerally applied over the whole design it will make it difficult to make achip that is competitive in power/performance compared to ARM/x86 CPUs.
> 
> 
> just the ALU pipeline registers.  we felt that the advantage of being ableto drop to say 500mhz and halve the number of pipeline stages to say 5, andalso be able to ramp up to 1.6ghz and double bavk up to 10 stages, wasworth considering.

What would be the advantage over running at 800Mhz with 5 pipeline stages ?

greets,
Staf.