[libre-riscv-dev] cache SRAM organisation

[Luke Kenneth Casson Leighton]

On Fri, Mar 27, 2020 at 9:40 AM Staf Verhaegen <staf at fibraservi.eu> wrote:
>
> Luke Kenneth Casson Leighton schreef op vr 27-03-2020 om 09:16 [+0000]:
> > On Fri, Mar 27, 2020 at 9:09 AM Staf Verhaegen <staf at fibraservi.eu> wrote:
> > > I still feel you intermix synchronous and write-through in this statement, the above seems to be possible with synchronous SRAMs.
> >
> > this would be good.  what would help clarify immensely is if you couldlet us know what options to nmigen Memory class are "supported".then it is really clear.
>
> The nmigen Memory abstraction does not seem to allow a good representation of a write-through SRAM. AFAICS it does not allow to have the output of the read port be changed by what you write on the write port.

urk, that's an important oversight.  we'll need to raise a bugreport
with whitequark about it.

jacob: was that other bug you found with nmigen Memory simulation ever fixed?

l.