[libre-riscv-dev] [Bug 186] Create decoder for SOC: Power ISA and RISC-V

[bugzilla-daemon at libre-riscv.org]

http://bugs.libre-riscv.org/show_bug.cgi?id=186

--- Comment #117 from Michael Nolan <mtnolan2640 at gmail.com> ---
(In reply to Luke Kenneth Casson Leighton from comment #115)

> 
> except one of the qemus is still running, thissays you have
> to call qemu_popen.communicate():
> https://docs.python.org/3/library/subprocess.html
> 
> fixed with a quick commit.

Oh, thank you! I was struggling to figure out where this was coming from.

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