[libre-riscv-dev] [Bug 186] Create decoder for SOC: Power ISA and RISC-V

[bugzilla-daemon at libre-riscv.org]

http://bugs.libre-riscv.org/show_bug.cgi?id=186

--- Comment #118 from Michael Nolan <mtnolan2640 at gmail.com> ---
(In reply to Luke Kenneth Casson Leighton from comment #116)
> i've also added pygdbmi to the dependencies in setup.py and added a way
> to get hold of and compile up powerpc64 gdb.  michael (and anyone else)
> could you take a look?
> https://git.libre-riscv.org/?p=soc.git;a=blob;f=README.md;hb=HEAD

Yep, that looks right

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