[libre-riscv-dev] [Bug 186] Create decoder for SOC: Power ISA and RISC-V

[bugzilla-daemon at libre-riscv.org]

http://bugs.libre-riscv.org/show_bug.cgi?id=186

--- Comment #116 from Luke Kenneth Casson Leighton <lkcl at lkcl.net> ---
i've also added pygdbmi to the dependencies in setup.py and added a way
to get hold of and compile up powerpc64 gdb.  michael (and anyone else)
could you take a look?
https://git.libre-riscv.org/?p=soc.git;a=blob;f=README.md;hb=HEAD

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