[libre-riscv-dev] Status on Our RISCV Implementation

Jacob Lifshay programmerjake at gmail.com
Tue Mar 24 17:44:05 GMT 2020

On Tue, Mar 24, 2020, 06:59 Luke Kenneth Casson Leighton <lkcl at lkcl.net>

> On Tue, Mar 24, 2020 at 1:11 PM Immanuel, Yehowshua U
> <yimmanuel3 at gatech.edu> wrote:
> > > nope.  not for RISC-V.  userspace only.
> >
> > So I guess we’d have a POWER kernel…
> correct.  and POWER TLBs and MMU.
> > If a binary tries to call RISCV instructions to set supervisor mode
> register - how is that handled?
> from userspace? fail... just like any other userspace RISC-V program
> is not permitted to set a supervisor mode register on any standard
> RISC-V system.

However, it's perfectly possible to have software that catches the illegal
instruction traps and emulates them, allowing running a RISC-V kernel.


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